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Features
* Compatible with MCS-51TM Products * 4K Bytes of Reprogrammable Flash Memory * * * * * * * * *
- Endurance: 1,000 Write/Erase Cycles 2.7V to 6V Operating Range Fully Static Operation: 0 Hz to 12 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes
Description
The AT89LV51 is a low-voltage, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory. The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard MCS-51TM instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89LV51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89LV51 operates at 2.7 volts up to 6.0 volts. (continued)
8-Bit Microcontroller with 4K Bytes Flash AT89LV51
Pin Configurations
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND
PDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
Not Recommended for New Designs. Use AT89LS51.
TQFP
(AD0) (AD1) (AD2) (AD3)
44 42 40 38 36 34 43 41 39 37 35
P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3
INDEX CORNER
(RXD) (TXD) (INT0) (INT1) (T0) (T1)
1 2 3 4 5 6 7 8 9 10 11
13 15 17 19 21 12 14 16 18 20 22
33 32 31 30 29 28 27 26 25 24 23
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
PLCC
(AD0) (AD1) (AD2) (AD3)
(WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
(RXD) (TXD) (INT0) (INT1) (T0) (T1)
P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5
6 4 2 44 42 40 1 3 4 3 4 13 9 75 8 38 9 37 36 10 35 11 34 12 33 13 32 14 31 15 16 30 1 7 1 9 2 1 2 3 2 5 2 72 9 18 20 22 24 26 28
(WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3
INDEX CORNER
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
0303D-D-12/97
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Block Diagram
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The AT89LV51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89LV51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89LV51 as listed below:
Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe)
Pin Description
VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups
Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. PSEN Program Store Enable is the read strobe to external program memory. When the AT89LV51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
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EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (V PP ) during Flash programming, when 12-volt programming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Table 1. AT89LV51 SFR Map and Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 SBUF XXXXXXXX PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 ACC 00000000 B 00000000
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 0 and 1 Timer 0 and Timer 1 in the AT89LV51 operate the same way as Timer 0 and Timer 1 in the AT89C51.
0FFH 0F7H 0EFH 0E7H 0DFH 0D7H TL2 00000000 TH2 00000000 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H TH0 00000000 TH1 00000000 PCON 0XXX0000 8FH 87H
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Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed Figure 1. Oscillator Connections
C2 XTAL2
C1 XTAL1
GND
Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Note:
C1, C2 = 30 pF 10 pF for Crystals = 40 pF 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
NC XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
GND
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Status of External Pins During Idle and Power Down Modes
Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
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Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:
Lock Bit Protection Modes (1)
Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U No program lock features. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. Same as mode 2, also verify is disabled. Same as mode 3, also external execution is disabled. Protection Type
3 4
P P
P P
U P
Note:
1.
The lock bits can only be erased with the Chip Erase operation.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Programming the Flash
The AT89LV51 is normally shipped with the on-chip Flash memory array in the erased state (i.e. contents=FFH) and ready to be programmed. The respective top-side marking and device signature codes are listed below:
VPP = 12V Top-Side Mark AT89LV51 xxxx yyww Signature (030H) = 1EH (031H) = 61H (032H) = FFH
The AT89LV51 code memory array is programmed byteby-byte. To program any non-blank byte in the on-chip Flash Code Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89LV51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89LV51, the following sequence should be followed: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89LV51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array and the lock bits are erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all "1"s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are: (030H) = 1EH indicates manufactured by Atmel (031H) = 61H indicates 89LV51 (032H) = FFH indicates 12V programming
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Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.
Flash Programming Modes
Mode Write Code Data RST H PSEN L ALE/PROG EA/VPP 12V P2.6 L P2.7 H P3.6 H P3.7 H
Read Code Data Write Lock Bit - 1
H H
L L
H
H 12V
L H
L H
H H
H H
Bit - 2
H
L
12V
H
H
L
L
Bit - 3
H
L
12V
H
L
H
L
Chip Erase
H
L
(1)
12V
H
L
L
L
Read Signature Byte Note:
H
L
H
H
L
L
L
L
1. Chip Erase requires a 10-ms PROG pulse.
Figure 3. Programming the Flash
+5V
Figure 4. Verifying the Flash
AT89LV51
A0 - A7 ADDR. OOOOH/OFFFH A8 - A11 SEE FLASH PROGRAMMING MODES TABLE P1 P2.0 - P2.3 P2.6 P2.7 P3.6 P3.7 XTAL2 EA VIH/VPP ALE PROG VCC P0 PGM DATA
CC
3-12 MHz
XTAL1 GND
RST PSEN
VIH
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Flash Programming and Verification Characteristics
TA = 0C to 70C, VCC = 5.0V 10%
Symbol VPP(1) IPP(1) 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL
(1)
Parameter Programming Enable Voltage Programming Enable Current Oscillator Frequency Address Setup to PROG Low Address Hold After PROG Data Setup to PROG Low Data Hold After PROG P2.7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold After PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float After ENABLE PROG High to BUSY Low Byte Write Cycle Time
Min 11.5
Max 12.5 25
Units V A MHz
3 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48t CLCL 10 10 1
12
s s 110 48t CLCL 48tCLCL s
tGLGH tAVQV tELQV tEHQZ tGHBL tWC Note:
0
48tCLCL 1.0 2.0 s ms
1. Only used in 12-volt programming mode.
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Flash Programming and Verification Waveforms (VPP = 12V)
P1.0 - P1.7 P2.0 - P2.3 PORT 0 tAVGL ALE/PROG tSHGL
VPP PROGRAMMING ADDRESS VERIFICATION ADDRESS
tAVQV
DATA IN DATA OUT
tDVGL
tGHDX
tGHAX tGHSL
LOGIC 1 LOGIC 0
tGLGH
EA/VPP tEHSH P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY)
tELQV
tEHQZ
BUSY
READY
tWC
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Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V DC Output Current...................................................... 15.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
TA = -40C to 85C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol VIL VIL1 VIH VIH1 VOL VOL1 VOH Parameter Input Low Voltage Input Low Voltage (EA) Input High Voltage Input High Voltage Output Low Voltage
(1)
Condition (Except EA)
Min -0.5 -0.5
Max 0.2 VCC - 0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.45 0.45
Units V V V V V V V V V V V V
(Except XTAL1, RST) (XTAL1, RST) (Ports 1,2,3) IOL = 1.6 mA IOL = 3.2 mA IOH = -60 A, VCC = 5V 10% IOH = -20 A IOH = -10 A
0.2 VCC + 0.9 0.7 VCC
Output Low (Port 0, ALE, PSEN)
Voltage (1)
Output High Voltage (Ports 1,2,3, ALE, PSEN)
2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -50 -650 10 50 300 10 20/5.5 5/1 100 20
VOH1
Output High Voltage (Port 0 in External Bus Mode)
IOH = -800 A, VCC = 5V 10% IOH = -300 A IOH = -80 A
IIL ITL ILI RRST CIO ICC
Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pulldown Resistor Pin Capacitance Power Supply Current
VIN = 0.45V VIN = 2V 0.45 < VIN < VCC
A A A K pF mA mA A A
Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz, VCC = 6V/3V Idle Mode, 12 MHz, VCC = 6V/3V
Power Down Mode
(2)
VCC = 6V VCC = 3V
Notes:
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V.
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AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
Symbol Parameter 12 MHz Oscillator Min 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low Data Valid to WR Transition Data Valid to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE High 43 200 203 23 433 33 0 123 tCLCL-40 0 97 517 585 300 3tCLCL-50 4tCLCL-130 tCLCL-60 7tCLCL-150 tCLCL-50 0 tCLCL+40 400 400 252 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 75 312 10 6tCLCL-100 6tCLCL-100 5tCLCL-165 0 59 tCLCL-8 5tCLCL-105 10 43 205 145 0 tCLCL-25 127 43 48 233 tCLCL-40 3tCLCL-45 3tCLCL-105 Max Variable Oscillator Min 0 2tCLCL-40 tCLCL-40 tCLCL-35 4tCLCL-100 Max 12 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
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External Program Memory Read Cycle
tLHLL ALE tAVLL PSEN tPLAZ tLLAX PORT 0
A0 - A7
tLLPL
tLLIV tPLIV
tPLPH
tPXAV tPXIZ tPXIX
INSTR IN A0 - A7
tAVIV PORT 2
A8 - A15 A8 - A15
External Data Memory Read Cycle
tLHLL ALE tWHLH PSEN tLLDV tLLWL RD tAVLL PORT 0 tLLAX tRLAZ
DATA IN
tRLRH
tRLDV
tRHDZ tRHDX
A0 - A7 FROM PCL INSTR IN
A0 - A7 FROM RI OR DPL
tAVWL tAVDV PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
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External Data Memory Write Cycle
tLHLL ALE tWHLH PSEN tLLWL WR tAVLL PORT 0 tLLAX tQVWX tWLWH
tQVWH
DATA OUT
tWHQX
A0 - A7 FROM PCL INSTR IN
A0 - A7 FROM RI OR DPL
tAVWL PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
VCC - 0.5V 0.7 VCC 0.2 VCC - 0.1V 0.45V
tCHCX tCLCH tCHCL
tCLCX tCLCL
External Clock Drive
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 83.3 20 20 20 20 Max 12 Units MHz ns ns ns ns ns
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Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 2.7V to 6V; Load Capacitance = 80 pF)
Symbol Parameter Min tXLXL tQVXH tXHQX tXHDX tXHDV Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1.0 700 50 0 700 12 MHz Osc Max Variable Oscillator Min 12tCLCL 10tCLCL-133 2tCLCL-117 0 10t CLCL-133 Max s ns ns ns ns Units
Shift Register Mode Timing Waveforms
INSTRUCTION ALE CLOCK 0 1 2 3 4 5 6 7 8
tXLXL tQVXH
WRITE TO SBUF
tXHQX
0 1 2 3 4 5 6 7 SET TI
VALID VALID VALID VALID VALID
OUTPUT DATA CLEAR RI INPUT DATA
tXHDV
VALID VALID
tXHDX
VALID
SET RI
AC Testing Input/Output Waveforms (1)
VCC - 0.5V 0.2 VCC + 0.9V TEST POINTS 0.45V 0.2 VCC - 0.1V
Float Waveforms (1)
V LOAD+ V LOAD V LOAD 0.1V 0.1V
V OL Timing Reference Points V OL +
0.1V
0.1V
Note:
1.
AC inputs during testing are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0".
Note:
1.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
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AT89LV51
ICC (mA)
24
VCC = 6.0 V
TYPICAL ICC (ACTIVE) at 25 C
o
20 16 12 8 4
VCC = 3.0 V VCC = 5.0 V
0
0 4 8 12 16 20 24
F (MHz)
AT89LV51
ICC (mA)
4.8
VCC = 6.0 V
TYPICAL ICC (IDLE) at 25 o C
4.0 3.2
2.4
1.6 0.8 0.0 0 4 8 12 16 20
VCC = 5.0 V
VCC = 3.0 V
24
F (MHz)
AT89LV51
TYPICAL ICC vs. VOLTAGE- POWER DOWN (85C)
20
I 15 C C
10
A5
0 3.0V
4.0V
5.0V
6.0V
Vcc VOLTAGE
Notes:
1. 2.
XTAL1 tied to GND for Icc (power down) Lock bits programmed
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Ordering Information
Speed (MHz) 12
Power Supply 2.7V to 6V
Ordering Code AT89LV51-12AC AT89LV51-12JC AT89LV51-12PC AT89LV51-12AI AT89LV51-12JI AT89LV51-12PI
Package 44A 44J 40P6 44A 44J 40P6
Operation Range Commercial (0 C to 70 C) Industrial (-40 C to 85 C)
12
2.7V to 6V
Package Type 44A 44J 40P6 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40 Lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
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